Within the communications industry, and in other industries more generally, it is desirable to adjustably attenuate a radio frequency (RF) signal without imparting a change to the phase of the attenuated signal. In particular, this is the case when RF signals are combined, for example, with signals at the output of a Doherty Amplifier circuit. Another example is when signals are combined to form a beam within a phased array system, such as might be used for either communications or radar. In the case of a Doherty Amplifier circuit, in order to properly combine the outputs of the two amplifiers that form a Doherty pair, the relative power from each amplifier must be adjusted. Such amplitude adjustment may be made using a digital step attenuator (DSA) at the output of one of the amplifiers before combining the outputs of each amplifier of the pair. When combining the outputs of the two amplifiers, it is important to control the relative phase of each signal to ensure that the signals combine as desired to meet a desired specification. In particular, it is typically important to maintain the same phase relationship between the two signals as changes are made to the amount of attenuation provided to the signals.
If the relative phase of a signal that is attenuated by the DSA changes when there are changes in the amount of attenuation applied, distortion typically occurs. For example, when combining the output of a Doherty pair, the output of a first amplifier is attenuated in order to properly set the relative amplitude level with respect to output of a second amplifier. If such changes in the amplitude cause changes in the relative phase of the signals being combined, QAM symbols modulated on the signal will be distorted making the signals difficult to demodulate.
FIG. 1 shows a digital step attenuator (DSA) 100 that might be used in a Doherty amplifier or other such circuit. The DSA 100 comprises several DSA cells 102-108. A signal is applied to the input 110 of the first cell 102. The cells 102-108 are coupled in series. Each cell 102-108 is in either a reference state or an attenuation state. In the reference state, the attenuation through the cell 102-108 is minimal. When a cell is in the attenuation state, the cell 102-108 will attenuate the signal by a predetermined amount. In one example, a “thermometer” configuration provides an equal amount of attenuation for each cell that is in the attenuation state. In this example, the total attenuation is equal to the sum of the attenuation provided by each of the cells that is in the attenuation state. In other thermometer configurations, different amounts of attenuation may be provided by each cell. Alternatively, in a “binary” controlled DSA with four cells and attenuation steps of n dB, the first cell 102 has an attenuation that is (20) n dB, the second cell 104 has an attenuation equal to (21) n dB, the third cell 106 has an attenuation of (22) n dB, and the fourth cell 108 has an attenuation of (23) n dB. Therefore, by selectively setting each cell to either the attenuation state or the reference state, a range of attenuation from the reference state to (24−1) n dB in n dB steps can be provided by the DSA 100.
FIG. 2 shows an integrated circuit (IC) layout of a typical cell (such as the cell 102 shown in FIG. 1). In one example, each cell 102-108 would have the same layout. The layout shows a resistor 202 coupled by a conductive trace 204 to an input pad 206 on one side. The other side of the resistor 202 is coupled by a conductive trace 208 to an output pad 210. A field effect transistor (FET) 214 is used as a control switch to control the state of cell 102. The FET 214 is used to place the cell 102 in either an attenuation state or a reference state. The source 212 of the FET 214 is coupled to the input pad 206. The drain 216 of the FET 214 is coupled to the output pad 210. When the FET 214 is turned on (i.e., conducts with minimal resistance from source 212 to drain 216), the cell 102 is in the reference state. When the FET 214 is turned off (i.e., has minimal conduction from source 212 to drain 216), the cell 102 is in the attenuation state.
A first capacitor 218 is coupled between the source 212 and a common potential, such as ground. Likewise, a second capacitor 220 is coupled between the drain 216 and a common potential, such as ground. The capacitors 218, 220 provide compensation for leakage through the parasitic capacitance through the FET 214. That is, at higher frequencies, signals will see lower impedance through the FET 214 than they do at relatively lower frequencies. Since it is desirable to maintain a flat amplitude response over the frequency band of interest, providing shunting capacitors 218, 220 will compensate for the reduced resistance through the FET 214 at relatively higher frequencies and thus allow for a relatively flat frequency response over the frequency band of interest.
However, while the amplitude frequency response is flat over the desired frequency range, the relative phase error is not. That is, as each cell 102-108 of the DSA 100 is switched from the reference state to the attenuation state in order to provide the desired attenuation, the relative phase of the output with respect to the input changes. The difference between the phase of the output when all cells are in the reference state and the phase of the output when a particular attenuation setting is selected is referred to herein as “relative phase error” for that particular attenuation setting.
FIG. 3 shows relative phase error with respect to frequency for several different attenuation settings of the DSA 100. The curves 302, 304, 306, 308 show the amount of phase error as a function of frequency for each of four different attenuation settings. For example, the curve 302 shows the relationship between phase error and frequency for an attenuation setting of approximately 15 dB. The curve 304 shows the relationship between phase error and frequency for an attenuation setting of approximately 10 dB. The curve 306 shows the relationship between phase error and frequency for an attenuation setting of approximately 5 dB. The curve 308 shows the relationship between phase error and frequency for an attenuation setting of approximately 0.5 dB.
In at least some applications in which a DSA 100 is used, it is desirable that the phase error not change when a particular DSA cell 102-108 is switched from the reference state to the attenuation state (i.e., when the level of attenuation for the DSA 100 changes). It is also desirable to maintain a relatively flat relative phase error over the desired operating frequency range. As noted above, distortion will occur in symbols modulated on an RF signal using quadrature amplitude modulation (QAM) if there is a significant difference in the relative phase error for signals that run through a DSA at one attenuation level with respect to another attenuation level. Such distortion can result in errors when demodulating the symbols (i.e., when trying to recover the information modulated on the signals). Furthermore, changes in the phase error over frequency at the same attenuation level are undesirable as well.
Accordingly, there is presently a desire for a DSA having cells with reduced relative phase error over a desired operating frequency range of interest and over a desired range of attenuation settings.